Bus driver having noise removing circuit formed by pull-up resistor

ABSTRACT

In a bus driver for driving a bus having first and second power supply terminals, an input terminal for receiving an input signal and an output terminal connected to the bus, a switching element is provided between the output terminal and the second power supply terminal, and the switching element is controlled by a voltage at the input terminal. A pull-up resistor is connected between the first power supply terminal and the output terminal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a bus driver for a data processing system.

[0003] 2. Description of the Related Art

[0004] In a data processing system, a plurality of packages each including a semiconductor integrated circuit are inserted into a back panel. The packages share buses formed on the back panel. In this case, each of the packages has a bus driver and a bus receiver.

[0005] A prior art bus driver includes an open drain type metal oxide semiconductor (MOS, broadly, metal insulating semiconductor (MIS)). This will be explained later in detail.

[0006] However, the prior art bus driver per se does not include a noise removing circuit, so that a large ringing effect is generated in the bus. Therefore, it takes a long time to converge the ringing effect, which substantially increases the propagation delay time of signals from the bus driver to its respective bus receivers. Also, it is difficult to increase the frequency of the propagated signals.

SUMMARY OF THE INVENTION

[0007] It is an object of the present invention to reduce the ringing effect in a bus driver, thus substantially reducing the signal propagation delay time as well as increasing the frequency of the propagated signals.

[0008] According to the present invention, in a bus driver for driving a bus having first and second power supply terminals, an input terminal for receiving an input signal and an output terminal connected to the bus, a switching element is provided between the output terminal and the second power supply terminal, and the switching element is controlled by a voltage at the input terminal. A pull-up resistor is connected between the first power supply terminal and the output terminal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings wherein:

[0010]FIG. 1 is a block circuit diagram illustrating a prior art data processing system;

[0011]FIG. 2 is a circuit diagram of the bus driver of FIG. 1;

[0012]FIG. 3 is an equivalent circuit diagram of the data processing system of FIG. 1;

[0013]FIG. 4 is a timing diagram showing the received signals at the bus receivers of FIG. 1;

[0014]FIG. 5 is a circuit diagram illustrating a first embodiment of the bus driver according to the present invention;

[0015]FIG. 6 is a circuit diagram illustrating a second embodiment of the bus driver according to the present invention;

[0016]FIG. 7 is a timing diagram showing the effect of the first and second embodiment;

[0017]FIG. 8 is an equivalent circuit diagram illustrating a data processing system including a third embodiment of the bus driver according to the present invention; and

[0018]FIG. 9 is a circuit diagram of the bus driver of FIG. 8.

DESCRIPTION OF THE PREFERRED EMBODIMETNS

[0019] Before the description of the preferred embodiments, a prior art bus driver will be explained with reference to FIGS. 1, 2, 3 and 4.

[0020] In FIG. 1, which illustrates a prior art data processing system, packages 100-1, 100-3, 100-4, . . . , 100-7 are inserted into a back panel 200 by connectors 101-1 and 101-2. In this case, a package 100-2 is not inserted into the back panel 200 intentionally, Thus, the packages 100-1, 100-3, 100-4, . . . , 100-7 share a bus 201 formed on the back panel 200.

[0021] One bus driver 102 is mounted on each of the packages 100-1, 100-3, 100-4, . . . , 100-7. The bus driver 102 is connected via a signal line 103 and the connector 101-1 to the bus 201. Also, one bus receiver (not shown) is mounted on each of the packages 100-1, 100-3, 100-4, . . . , 100-7. The bus receiver is connected via a signal line (not shown) and the connector 101-2 to the bus.

[0022] In FIG. 2, which is a circuit diagram of the bus driver 102 of FIG. 1, the bus driver 102 is formed by an open drain type MOS transistor having a gate for receiving an input voltage V_(in), a grounded source and a drain for generating an output voltage V_(out.) That is, the bus driver of FIG. 2 does not have a noise removing circuit.

[0023] In FIG. 3, which is an equivalent circuit diagram of the system of FIG. 1, the spacing between the packages depends upon the height of heat sinks of semiconductor integrated devices mounted thereon. For example, the spacing between the packages 101-1 and 101-2 (in this case, the package 101-2 is removed) is 1.4 inches; the spacing between the packages 101-2 and 101-3 is 2.0 inches; the spacing between the packages 101-3 and 101-4 is 1.8 inches; the spacing between the packages 101-4 and 101-5 is 1.8 inches; the spacing between the packages 101-5 and 101-6 is 2.0 inches; and the spacing between the packages 101-6 and 101-7 is 1.0 inches. Also, the length of a stub of each of the packages i.e., the distance between the connector 101-1 and each of the bus drivers is 1 inch. Further, a terminal resistor R formed on the back panel 200 is connected to the connector 101-1 of each of the packages 101-1 and 101-7.

[0024] In FIG. 3, when the input voltage V_(in) of the bus driver 102 included in the package 101-3 is switched from high to low and vice versa, the voltages at the bus receivers at the packages 101-1, 101-3, 101-4, . . . , 101-7 are obtained as shown in FIG. 4. As shown in FIG. 4, a large ringing effect is generated in each of the voltages of the bus receivers since the bus driver 102 does not have a noise removing circuit. That is, it takes longer than 40 ns to converge the voltages at the bus receivers. This substantially increases the signal propagation delay time, and also it is difficult to increase the frequency of the propagated signals.

[0025] Note that each bus receiver of the packages 101-1, 101-3, 101-4, 101-5, 101-6 and 101-7 had the same configuration as the bus driver of FIG. 2.

[0026] In FIG. 5, which illustrates a first embodiment of the bus driver according to the present invention, the bus driver includes a MOS transistor 1 as a switching element having a gate connected to an input terminal IN for receiving an input voltage V_(in,) a drain connected to an output terminal OUT for generating an output voltage V_(out,) and a source connected to the ground terminal GND. Also, the bus driver includes a noise removing circuit formed by a pull-up resistor 2-1.

[0027] In FIG. 6, which illustrates a second embodiment of the bus driver according to the present invention, the bus driver includes a bipolar transistor 1′ instead of the MOS transistor 1 of FIG. 5. The bipolar transistor 1′ has a base connected to the input terminal IN, a collector connected to the output terminal OUT, and an emitter connected to the ground terminal GND. The bus driver of FIG. 6 operates in the same way as the bus driver of FIG. 5.

[0028] Assume that the bus driver of FIG. 5 or 6 is applied to the data processing system of FIGS. 1 and 3. In this case, when the input voltage V_(in,) of the bus driver of FIG. 5 or 6 included in the package 101-3 is switched from high to low and vice versa, the voltages at the bus receivers at the packages 101-1, 101-3, 101-4, . . . , 101-7 are obtained as shown in FIG. 7. As shown in FIG. 7, the ringing effect generated in each of the voltages of the bus receivers is reduced, since the bus driver of FIG. 5 or 6 has a noise removing circuit formed by the pull-up resistor 2. Therefore, it takes less than 20 ns to converge the voltages at the bus receivers. This substantially decreases the signal propagation delay time, and also, the frequency of the propagated signals can be increased.

[0029] In FIG. 8, which illustrates a third embodiment of the present invention, one pull-up resistor R′ formed on the back panel 200 is connected to the connector 101-1 of each of the packages 101-2, 101-3, 101-4, 101-5 and 101-6 of FIG. 3. Note that each of the packages 101-1, 101-3, 101-4, 101-5, 101-6 and 101-7 includes an open drain type MOS transistor as a bus driver or a bus receiver as illustrated in FIG. 2; however, this bus driver or bus receiver can be an open collector type bipolar transistor as illustrated in FIG. 9.

[0030] In FIG. 8, when the input voltage V_(in,) of the bus driver included in the package 101-3 is switched from high to low and vice versa, the voltages at the bus receivers at the packages 101-1, 101-3, 101-4, . . . , 101-7 are obtained in a similar way to that of FIG. 7. That is , the ringing effect generated in each of the voltages of the bus receivers is reduced, since packages 101-2, 101-3, 101-4 101-5, 101-6 has a noise removing circuit formed by the pull-up resistor R′. Therefore, it takes less than 20 ns to converge the voltages at the bus receivers. This substantially decreases the signal propagation delay time, and also, the frequency of the propagated signals can be increased.

[0031] In the data processing system of FIG. 8, each of the packages 101-1, 101-3, 101-4, 101-5, 101-6 and 101-7 includes an open drain type bus driver or an open collector type bus driver; however, the bus driver as illustrated in FIG. 5 or 6 can be used as such a bus driver.

[0032] As explained hereinabove, according to the present invention, the signal propagation delay time can be reduced, and also, it is easy to increase the frequency of the propagated signals. 

1. A bus driver for driving a bus comprising: first and second power supply terminals; an input terminal for receiving an input signal; an output terminal connected to said bus; a switching element, connected between said output terminal and said second power supply terminal, said switching element being controlled by a voltage at said input terminal; and a pull-up resistor, connected between said first power supply terminal and said output terminal.
 2. The bus driver as set forth in claim 1 , wherein said switched element comprises a MIS transistor.
 3. The bus driver as set forth in claim 1 , wherein said switching element comprises a bipolar transistor.
 4. A bus driver for driving a bus, comprising: a first power supply terminal for receiving a first voltage; a second power supply terminal for receiving a second voltage lower than said first voltage; an input terminal; an output terminal connected to said input terminal; a MIS transistor having a gate connected to said input terminal, a drain connected to said output terminal and a source connected to said second power supply terminal; and a resistor connected between said first power supply terminal and the drain of said MIS transistor.
 5. A bus driver for driving a bus, comprising: a first power supply terminal for receiving a first voltage; a second power supply terminal for receiving a second voltage lower than said first voltage; an input terminal; an output terminal; a bipolar transistor having a base connected to said input terminal, a collector connected to said output terminal and an emitter connected to said second power supply terminal; a resistor connected between said first power supply terminal and the collector of said bipolar transistor.
 6. A data processing system comprising: a power supply line; a plurality of connectors; a plurality of noise absorption means each connected to one of said connectors and said power supply line; and a plurality of bus drivers each connected to one of said connectors.
 7. The system as set forth in claim 6 , wherein each of said noise absorption means comprises a resistor.
 8. The system as set forth in claim 6 , wherein each of said bus drivers comprises an open drain type MIS transistor.
 9. The system as set forth in claim 6 , wherein each of said bus drivers comprises an open drain type bipolar transistor.
 10. The system as set forth in claim 6 , wherein each of said bus drivers comprises: first and second power supply terminals; an input terminal for receiving an input signal; an output terminal connected to one of said connectors; a switching element, connected between said output terminal and said second power supply terminal, said switching element being controlled by a voltage at said input terminal; and a pull-up resistor, connected between said first power supply terminal and said output terminal.
 11. The system as set forth in claim 10 , wherein said switched element comprises a MIS transistor.
 12. The bus driver as set forth in claim 10 , wherein said switching element comprises a bipolar transistor.
 13. A data processing system comprising: a back panel; a power supply line provided in said back panel; a plurality of packages each including a connector capable of being connected to said power supply line and a bus driver connected to said connector; and a plurality of resistors each connected between the connector of one of said packages and said power supply line.
 14. The system as set forth in claim 13 , wherein said resistors are provided on said back panel.
 15. The system as set forth in claim 13 , wherein said bus driver comprises an open drain type MIS transistor.
 16. The system as set forth in claim 13 , wherein said bus driver comprises an open drain type bipolar transistor.
 17. The system as set forth in claim 13 , wherein said bus driver comprises: first and second power supply terminals; an input terminal for receiving an input signal; an output terminal connected to said connector; a switching element, connected between said output terminal and said second power supply terminal, said switching element being controlled by a voltage at said input terminal; and a pull-up resistor, connected between said first power supply terminal and said output terminal
 18. The system as set forth in claim 17 , wherein said switching element comprises a MIS transistor.
 19. The bus driver as set forth in claim 17 , wherein said switching element comprises a bipolar transistor. 